Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a local decoder in a semiconductor memory device having a divided word line structure, which is used in a Static Random Access Memory (SRAM) and the like.
In a semiconductor memory device such as an SRAM and a Dynamic Random Access Memory (DRAM) having a large-scale memory array, a so-called xe2x80x9cdivided word line structurexe2x80x9d is known that is directed to suppress delay in signal propagation on a word line and to reduce the circuit scale of a decode circuit effecting word line selection. An example of the divided word line structure is disclosed in Japanese Patent Laying-Open No. 59-72695 (hereinafter also referred to as xe2x80x9cConventional Example 1xe2x80x9d).
FIGS. 5 and 6 are the first and second conceptual diagrams each illustrating a divided word line structure shown in Conventional Example 1.
A semiconductor memory device shown in FIG. 5 includes a memory array divided into four memory blocks 5a to 5d, a global decoder 10, and local decoder zones 20a to 20d provided in correspondence to memory blocks 5a to 5d, respectively. Memory cells MC are arranged in a matrix of rows and columns in each of memory blocks 5a to 5d. A word line WL is arranged in correspondence to each of the memory cell rows, whereas a bit line pair BLP constituted by complementary bit lines BL and /BL is arranged in correspondence to each of the memory cell columns.
A global word line GWL is provided common to memory blocks 5a to 5d along a longitudinal direction (row direction) of a chip. Each word line WL is separately arranged in each of memory blocks 5a to 5d. Global decoder 10 is arranged at a middle portion of the memory array, i.e., between memory blocks 5b and 5c, to control activation of global word line GWL. Local decoder zone 20a arranged at memory block 5a to control activation of word line WL and local decoder zone 20b arranged at memory block 5b to control activation of word line WL are locally arranged at the border of memory blocks 5a and 5b. Likewise, local decoder zone 20c arranged at memory block 5c to control activation of word line WL and local decoder zone 20d arranged at memory block 5d to control activation of word line WL are locally arranged at the border of memory blocks 5c and 5d. 
In a semiconductor memory device shown in FIG. 6, global decoder 10 is arranged in correspondence to an end of a memory array constituted by memory blocks 5a to 5d. The other parts are structured as in the semiconductor memory device shown in FIG. 5.
In each of the semiconductor memory devices shown in FIGS. 5 and 6, memory cell MC is provided with a xe2x80x9cSRAM cellxe2x80x9d represented by e.g. a high resistance load N-MOS (Metal Oxide Semiconductor) memory cell shown in FIG. 7, a TFT (Thin-Film Transistor) load memory cell shown in FIG. 8, and a CMOS (Complementary MOS) memory cell shown in FIG. 9.
Referring to FIG. 7, memory cell MC of a high resistance load N-MOS memory cell includes N-channel MOS transistors 31 and 32 each having a gate connected to a corresponding word line WL, a high resistance loads 34 and 35 connected between a power-supply voltage Vcc and respective nodes Ns and /Ns, and N-channel MOS transistors 36 and 37 connected between respective nodes Ns and /Ns and a ground voltage Vss. Nodes Ns and /Ns are electrically coupled to complimentary bit lines BL and /BL, respectively, via transistors 31 and 32.
Nodes Ns and /Ns are connected to bit lines BL and /BL, respectively, in response to word line WL being activated (to a high level). This allows data on bit lines BL and /BL to be written into respective nodes Ns and /Ns. Once the data is written, it is held by transistors 36 and 37 that are complementarily turned on, and by high resistance loads 34 and 35, during power input.
It is noted that, in the present description, a high-voltage state (high level) and a low-voltage state (low level) of each signal line, signal, data and the like that are set in binary are also simply referred to as xe2x80x9cHxe2x80x9d level and xe2x80x9cLxe2x80x9d level, respectively.
Referring to FIG. 8, in a memory cell MC of a TFT load memory cell, TFT loads 41 and 42 formed by P-type thin-film transistors (TFT) are arranged in place of high resistance loads 34 and 35 in the structure of the high resistance load N-MOS memory cell shown in FIG. 7. This prevents through current from flowing between power-supply voltage Vcc and ground voltage Vss via nodes Ns or /Ns, reducing power consumption at the memory cell.
Referring to FIG. 9, in a memory cell MC of a CMOS memory cell, P-channel MOS transistors 45 and 47 are provided in place of high resistance loads 34 and 35, respectively, in the structure of high resistance load N-MOS memory cell shown in FIG. 7. The CMOS memory cell is known as having a highly stable structure with a large operation margin.
FIG. 10 is a circuit diagram illustrating a structure of a local decoder zone in the divided word line structure. In FIG. 10, local decoder zones 20a and 20b of local decoder zones 20a to 20d shown in FIGS. 5 and 6 are representatively illustrated.
Referring to FIG. 10, it is assumed that four word lines WL, associated with one global word line GWL, are arranged in each of memory blocks 5a to 5d. 
Local decoder control circuit 15 generates a word line selection signal that is associated with each one of the four word lines associated with one global word line GWL. The word line selection signal is independently generated at each of memory blocks 5a to 5d, to control selection from each set of four word lines associated with one global word line GWL. Local decoder control circuit 15 generates word line selection signals WSa0 to WSa3 to be associated with memory block 5a, and word line selection signals WSb0 to WSb3 to be associated with memory block 5b. 
Local decoder control circuit 15 selectively activates one of the four word line selection signals associated with a selected memory block, and inactivates the remaining word line selection signals. In addition, word line selection signals associated with a non-selected memory block are inactivated. For instance, when memory block 5a is selected, one of word line selection signals WSa0 to WSa3 is selectively activated, while the remaining word line selection signals are inactivated.
Though not shown, word line selection signals are generated similarly for each of memory blocks 5c and 5d. In the description below, word line selection signals WSa0 to WSa3, WSb0 to WSb3, . . . are also simply referred to as, collectively, a word line selection signal WS.
A local decoder 50 is arranged in correspondence to each word line WL. Local decoder 50 activates or inactivates a corresponding word line WL in accordance with the voltage of a corresponding word line selection signal WS and a corresponding global word line GWL. Various structures have conventionally been proposed for such a local decoder which is one kind of row decoder.
Local decoder 50 arranged at local decoder zone 20a includes, for example, an NAND gate producing the result of an NAND logical operation of the voltage level of a corresponding one of word line selection signals WSa0 to WSa3 and the voltage level of a corresponding global word line GWL, and an inverter driving the voltage of a corresponding word line WL in accordance with an output of the NAND gate.
FIG. 11 is a circuit diagram showing the first configuration example of a local decoder according to the conventional technique.
Referring to FIG. 11, local decoder 50 according to the conventional technique includes P-channel MOS transistors 51 and 52 connected in parallel between power-supply voltage Vcc and node N0, N-channel MOS transistors 53 and 54 connected in series between node N0 and ground voltage Vss, and an inverter 55 driving word line WL with one of power-supply voltage Vcc and ground voltage Vss in accordance with the inversion level of the voltage of node N0.
Each gate of transistors 52 and 53 is connected to node N1, whereas each gate of transistors 51 and 54 is connected to node N2. One of nodes N1 and N2 is connected to a corresponding global word line GWL, while the other one of nodes N1 and N2 receives a corresponding word line selection signal WS. Local decoder 50 shown in FIG. 11 is also referred to as an xe2x80x9cNAND decoder.xe2x80x9d In local decoder 50 corresponding to a word line to be activated, both nodes N1 and N2 are set at the H level (e.g. power-supply voltage Vcc). Thus, local decoder 50 connects the word line to be activated to power-supply voltage Vcc, while connecting the word line to be inactivated to ground voltage Vss.
In the present description, the operation for raising word line WL from the L level (e.g. ground voltage Vss) to the H level (e.g. power-supply voltage Vcc) will be referred to as xe2x80x9cactivation of word line,xe2x80x9d and the operation for lowering word line WL from the H level to the L level will be referred to as xe2x80x9cinactivation of word line.xe2x80x9d In addition, the operation for selectively activating or inactivating each word line is also referred to as xe2x80x9cactivation control of word line.xe2x80x9d
FIG. 12 is a circuit diagram showing the second configuration example of a local decoder according to the conventional technique.
Referring to FIG. 12, a local decoder 60 according to the conventional technique includes P-channel MOS transistors 61 and 62 connected in series between power-supply voltage Vcc and word line WL, and N-channel MOS transistors 63 and 64 connected in parallel between word line WL and ground voltage Vss. Each gate of transistors 61 and 63 is connected to node N1, and each gate of transistors 62 and 64 is connected to node N2. Local decoder 60 is also referred to as an xe2x80x9cNOR decoder.xe2x80x9d In the local decoder corresponding to a word line to be activated, both nodes N1 and N2 are set at the L level (e.g. ground voltage Vss).
Compared with local decoder 50 of an NAND type shown in FIG. 11, such local decoder 60 of an NOR type can be reduced in the number of circuit elements therein, allowing reduction of the circuit area. In local decoder 60, however, word line WL must be directly driven by transistors 61 to 64, which requires these transistors to have relatively large current drivability (transistor size). This increases the gate capacitance of each transistor, which in turn increases the load capacitance of nodes N1 and N2 corresponding to an input terminal of local decoder 60, making it difficult to increase the speed of activation control of word lines.
A structure of a local decoder that can be reduced in size and increased in operation speed is further disclosed in Aizaki S., et al. xe2x80x9cA 15 ns 4 Mb CMOS SRAMxe2x80x9d ISSCC DIGEST OF TECHNICAL PAPERS, pp. 126-127; February 1990 (hereinafter also referred to as xe2x80x9cConventional Example 2xe2x80x9d).
FIG. 13 is a circuit diagram showing the structure of a local decoder according to the conventional technique described in Conventional Example 2.
Referring to FIG. 13, a local decoder 70 shown in Conventional Example 2 includes an N-channel MOS transistor 71 electrically coupled between nodes N0 and N2, P-channel MOS transistor 73 electrically coupled between power-supply voltage Vcc and node N0, and an inverter 75 for driving word line WL with one of power-supply voltage Vcc and ground voltage Vss in accordance with the inversion level of the voltage of node N0. The size (current drivability) of transistor 73 is designed to be smaller than the size (current drivability) of transistor 71.
The gate of transistor 71 is connected to node N1. The gate of transistor 73 is connected to ground voltage Vss, setting transistor 73 in a normally-on state. One of nodes N1 and N2 is connected to global word line GWL, while the other one of nodes N1 and N2 receives a corresponding word line selection signal WS.
When word line WL is inactivated, in a corresponding local decoder 70, node N1 is set at the L level (ground voltage Vss) while transistor 71 is turned off. In such a state, node N0 is charged to power-supply voltage Vcc by transistor 73 in the normally-on state, so that inverter 75 connects a corresponding word line WL to ground voltage Vss to inactivate the word line WL.
When word line WL is activated, in a corresponding local decoder 70, node N1 is set at the H level (power-supply voltage Vcc) to turn on transistor 71 and then node N2 is set at the L level (ground voltage Vss). In this state, through current represented by the arrow in the drawings, which flows from power-supply voltage Vcc via transistors 71 and 73 to node N2 set at the L level, drives node N0 toward ground voltage Vss. Accordingly, inverter 75 connects a corresponding word line WL with power-supply voltage Vcc to activate the word line WL.
Such local decoder 70 can be configured with a smaller number of circuit elements compared to local decoder 50 of an NAND type. Furthermore, the current drivability (transistor size) of transistor 71 can be smaller than the current drivability (transistor size) of each of transistors 53 and 54 connected in series in local decoder 50, for attaining approximately the same drivability for node N0. This can also reduce the load capacitance of nodes N1 and N2, resulting in faster activation control of word line WL compared to local decoder 50. As such, local decoder 70 can realize further reduction of the circuit area and faster operation, compared to local decoders 50 and 60 shown in FIGS. 11 and 12 respectively.
In local decoder 70, word line WL is inactivated by charging node N0 by normally-on transistor 73 having relatively small drivability. This makes inactivation speed, i.e. lowering speed, of word line WL slower. Such a problem has been solved by the structure of a local decoder that can lower a word line at a high speed, which is disclosed in Japanese Patent Laying-Open No. 4-143995 (hereinafter also referred to as xe2x80x9cConventional Example 3xe2x80x9d).
FIG. 14 is a circuit diagram showing the structure of a local decoder 80 according to the conventional technique shown in Conventional Example 3.
Referring to FIG. 14, local decoder 80 shown in Conventional Example 3 further includes a P-channel MOS transistor 85 connected in parallel with transistor 73, in addition to transistors 71, 73 and inverter 75 that are arranged as in local decoder 70 shown in FIG. 13. The gate of transistor 85 is connected to node N1 as in the gate of transistor 71. Thus, transistors 71 and 85 are complimentarily turned on and off in accordance with the level of node N1.
Local decoder 80 charges node N0 by both transistors 73 and 85 when node N1 is changed from the H level to the L level to inactivate a corresponding word line WL, so that word line WL can be inactivated at a speed higher than that in local decoder 70. Word line WL is activated at a high speed, similarly to local decoder 70.
As such, the structure of local decoders 70 and 80 disclosed in Conventional Examples 2 and 3, respectively, can be used as a local decoder in order to effectuate both a smaller local decoder and faster activation control of word lines.
A semiconductor memory device, however, requires a defect acceleration test (hereinafter also referred to as a xe2x80x9cburn-in testxe2x80x9d) to be performed that accelerates a potential initial defect to screen a chip in order to ensure operation reliability. In the burn-in test, high-field stress is applied to a wafer, i.e. chip, that went through the manufacturing process, to elicit such a potential defect.
At the burn-in test, time required for the test per chip must be shortened. Therefore, the burn-in test employs such a structure that a plurality of word lines are activated in parallel within a semiconductor memory device in response to a specific control signal input at the test. In particular, a technique for efficiently eliciting a potential failure in a short period of time by activating all word lines in every even-numbered or odd-numbered rows.
In the local decoders shown in FIGS. 13 and 14 respectively, however, through current flows at activation, i.e. raising, of word line WL, increasing the operating current if a number of word lines are raised at the same time in the burn-in test. This is significant in a large scale semiconductor memory device. In an extreme case, the chip itself may generate heat. If the number of chips that can be mounted at once on a test board for the burn-in test needs to be limited in consideration of operating peak current efficiency of the burn-in test will be lowered.
An object of the present invention is to provide a semiconductor memory device with a simple structure that controls activation of a word line at a high speed in normal operation, and that includes a local decoder having a circuit configuration capable of suppressing operating current in a burn-in test.
According to an aspect of the present invention, a semiconductor memory device includes a plurality of memory cells, a plurality of global word lines, a plurality of word lines, a global decoder, a plurality of local decoder selection circuits, K (K: natural number) selection signal lines, a plurality of local decoders, and a control circuit.
The plurality of memory cells are arranged in rows and columns, and divided into a plurality of blocks along a column direction. Each of the plurality of global word lines are arranged at every K (K: natural number) memory cell rows, to be common to the plurality of blocks. The plurality of word lines are separately arranged for each of the memory rows in correspondence to the plurality of blocks, respectively. The global decoder sets a voltage of the plurality of global word lines in accordance with the result of row selection. The plurality of local decoder selection circuits are provided in correspondence to the plurality of blocks respectively, each generating K selection signals associated with respective ones of K word lines associated with each of the global word lines, in accordance with selection information of the plurality of blocks and the result of row selection. K selection signal lines are provided for each of the blocks, to transmit the K selection signals from a corresponding one of the plurality of local decoder selection circuits, respectively. The plurality of local decoders are provided in correspondence to the plurality of word lines respectively, each controlling activation of corresponding one of the word lines in accordance with a voltage of a corresponding one of the K selection signal lines and a voltage of a corresponding one of the plurality of global word lines. Each of the local decoders includes a first switch circuit connecting, in accordance with a voltage of a first node connected to one of the corresponding selection signal line and a corresponding one of the global word lines, a second node connected to the other one of the corresponding selection signal line and the corresponding global word line with an internal node, a driver circuit to set the corresponding word line in an activated state when the internal node is set at a first voltage via the first switch circuit, and to set the corresponding word line in an inactivated state when the internal node is set at a second voltage, and a second switch circuit to connect the internal node with the second voltage. A control circuit turns off the second switch circuit, in another operation mode different from a normal operation mode, where multiple ones of said plurality of word lines are simultaneously activated, in the local decoder corresponding to each of the simultaneously activated plurality of word lines.
Preferably, another operation mode corresponds to a burn-in test.
Therefore, a primary advantage of the present invention is to prevent through current from flowing between the second node and the second voltage in an operation mode where a plurality of word lines are simultaneously activated. As a result, for example, operating peak current can be suppressed in the operation mode corresponding to the burn-in test.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.